The present invention generally relates to a method of fabricating a memory device and, more particularly, to a method of fabricating a NAND flash device.
In a NAND flash device, a common-source-line contact may be disposed beside NAND strings for source line pick-up, while a plurality of drain contacts and bit-line contact plugs may be disposed for electrically coupling a common drain region of the NAND strings with the bit lines. To ensure electrical connection, each of the bit-line contact plugs is required to overlay and vertically aligned with a corresponding one of the drain contacts, and hence a complex lithography process may be needed. However, mis-alignment between the bit-line contact plugs (also termed “via0”) and the drain contacts (also termed “contact”) may occur, as will be discussed below.
FIGS. 1A to 1J are schematic cross-sectional views illustrating a method of manufacturing a NAND flash device in prior art. Throughout FIGS. 1A to 1J, only parts of the NAND flash device are shown for simplicity. Referring to FIG. 1A, a substrate 10 may be provided. A NAND string 11, a source select gate 112, a drain select gate 113, a common source region 11a and a common drain region 11b, which are electrically coupled with one another in series and arranged in a first reference direction, i.e., a direction horizontally across the plane of the page of the diagram of FIG. 1A, may be formed on the substrate 10. A first dielectric layer 12 with a height T1 may be formed on the NAND string 11, the source select gate 112, the drain select gate 113, the common source region 11a and the common drain region 11b by a deposition process. The first dielectric layer 12 may include a dielectric material such as silicon oxide (SiO2) or silicon oxynitride (SiON). A patterned first mask layer 13 of photo-resist with a first opening 131 and a plurality of second openings 132 may be formed on the first dielectric layer 12. The first opening 131 may extend in a second reference direction, i.e., a direction perpendicular to the plane of the page of the diagram of FIG. 1A. Furthermore, the second openings 132 may be arranged in an array extending in the second reference direction.
Referring to FIG. 1B, a first trench 121 and a plurality of first holes 122 may be formed into the first dielectric layer 12 through the first opening 131 and the second openings 132, respectively, by a dry etch process using the patterned first mask layer 13 as a mask. After the trench-forming process, the patterned first mask layer 13 may then be removed by a strip process.
Referring to FIG. 1C, a conductive material such as tungsten (W) may be deposited on the surface of the first dielectric layer 12, the first trench 121 and the first holes 122 by a chemical vapor deposition (CVD) process, filling the first trench 121 to form a first contact structure 141 and filling the first holes 142 to form a plurality of second contact structures 142. The first contact structure 141 and each of the second contact structures 142 may have a height equal to T1. A first conductive layer 14 of the conductive material may then be formed thereon.
Referring to FIG. 1D, the first conductive layer 14 may be removed by a chemical-mechanical polish (CMP) process using the first dielectric layer 12 as a polish-stopping layer, exposing top of the first contact structure 141 and top of the second contact structures 142.
Referring to FIG. 1E, a second dielectric layer 15 with a height T2 may be formed on the first dielectric layer 12 by a deposition process. The second dielectric layer 15 may include the same dielectric material as the first dielectric layer 12, and hence the second dielectric layer 15 may then be merged with the first dielectric layer 12 to form a third dielectric layer 16, as shown in FIG. 1F. The third dielectric layer 16 may serve as an inter layer dielectric (ILD) layer.
Referring to FIG. 1F, a patterned second mask layer 17 of photoresist with a plurality of third openings 171 may be formed on the third dielectric layer 16 by a lithography process. The third openings 171 may be arranged in an array extending in the second reference direction. Each of the third openings 171 is vertically aligned with a corresponding one of the second contact structures 142. The critical dimension of each of the third openings 171 is smaller than that of the top surface of each of the second contact structures 142.
Referring to FIG. 1G, a plurality of second holes 161 may be formed into the third dielectric layer 16 through the third openings 171 by a dry etch process using the patterned second mask layer 17 as a mask. Since the third openings 171 with a smaller critical dimension are vertically aligned with the second contact structures 142, each of the second holes 161 may expose a portion of a corresponding one of the second contact structures 142. After the hole-forming process, the patterned second mask layer 17 may then be removed.
Referring to FIG. 1H, a conductive material same as that of the first conductive layer 14 may be deposited on the third dielectric layer 16, filling the second holes 161 to form a plurality of third contact structures 181. Each of the third contact structures 181 may have a height equal to T2 and may overlay the corresponding one of the second contact structures 142. A second conductive layer 18 of the conductive material may then be formed on the third dielectric layer 16.
Referring to FIG. 1I, the second conductive layer 18 may be removed by a CMP process using the third dielectric layer 16 as a polish-stopping layer. Top of the third contact structures 181 may be exposed thereafter.
Referring to FIG. 1J, a patterned metal layer 19 may be formed on the third dielectric layer 16 and the third contact structures 181. The patterned metal layer 19 may include bit lines extending in parallel in the first reference direction. Each of the third contact structures 181 may serve as a bit-line contact plug, which electrically couples one of the second contact structures 142 to one of the bit lines, while each of the second contact structures 142 may serve as a drain contact, which electrically couples the corresponding bit-line contact plug to the common drain region 11b. The first contact structure 141 which is electrically coupled with the common source region 11a may serve as a common-source line contact for source line pick-up.
With the increasing interest in compact and low-profile electronic products, the critical dimensions of the third openings 171 and the third contact structures 181 may be so small that process window will be a concern without high-resolution exposure tool. Furthermore, the third contact structures 181 and the second contact structures 142 are formed by two individual steps, which may increase the risk of mis-alignment without high-precision exposure tool. It may therefore be desirable to have a method that is able to manufacture semiconductor memory devices in a simplified process and alleviate the mis-alignment issue.